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This circuit provides a self power-up function for a capacitive load such as a read-only memory and eliminates the need for a separate charge or restore input during power-up and between reading operations.
English (United States)
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Self Power Up Driver for Read Only Memory
This circuit provides a self power-up function for a capacitive load such as a
read-only memory and eliminates the need for a separate charge or restore input
during power-up and between reading operations.
During the initial power-up of the memory, supply VDD goes from ground to
its positive level, say, 5 volts. Node 8 rises rapidly to 5 volts because of a small
time constant of the path through depletion FET T10 and the gates of FETs T1
and T4. Nodes C and 1 also rise rapidly because of a small time constant
through depletion devices TB and T1 (which is turned on by the rise of node 8)
and the gates of devices T2 and T3.
As node 1 rises, T2 and T3 are caused to conduct, bringing the node marked
OUTPUT from ground toward the 5-volt level. The voltage rise at node C also
turns on depletion device TH, supporting the charging of the OUTPUT node.
Node 4 remains at ground level during this portion of the operating cycle because
T4 is designed with a much greater width-to-length value than T2, and turns on
The increasing level at node 1 turns T3 on harder over time until the
OUTPUT node rises above the threshold of device T5, at which time a path to
ground is established through T5 and node 8 rapidly falls to ground level.
As node 8 goes to ground, T4 is turned rapidly off and node 4 rises to 5 volts.
The gate of T1 is also discharged to ground when node 8 falls so that T1 is
turned completely off. This allows bootstrapping driv...