Browse Prior Art Database

Double Port Register Chip Using Single Port Cells

IP.com Disclosure Number: IPCOM000051477D
Original Publication Date: 1981-Jan-01
Included in the Prior Art Database: 2005-Feb-10

Publishing Venue

IBM

Related People

Authors:
Brantley, WC Dachtera, W [+details]

Abstract

In a two address vector instruction the destination register is both read and written for each element of the vector. If a vector processor is pipelined so that one element of the result is produced per cycle, then the destination register must be read and written in the same cycle. This article describes an arrangement which allows the register to be both read and written in the same cycle without requiring that the register be made up of double-port cells.