Browse Prior Art Database

Reduced Bit Line Capacitance in VMOS Devices

IP.com Disclosure Number: IPCOM000051528D
Original Publication Date: 1981-Feb-01
Included in the Prior Art Database: 2005-Feb-10

Publishing Venue

IBM

Related People

Authors:
Kenney, DM [+details]

Abstract

When polysilicon word and bit lines of a VMOS memory cell cross in the V-groove, the bit line capacitance is reduced substantially by providing a thick dielectric material in the V-groove between the word and bit lines by utilizing a spin-on technique.