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Reduced Bit Line Capacitance in VMOS Devices Disclosure Number: IPCOM000051528D
Original Publication Date: 1981-Feb-01
Included in the Prior Art Database: 2005-Feb-10

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Kenney, DM [+details]


When polysilicon word and bit lines of a VMOS memory cell cross in the V-groove, the bit line capacitance is reduced substantially by providing a thick dielectric material in the V-groove between the word and bit lines by utilizing a spin-on technique.