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Partial Parity Predict for CPU having Architectural Rotate and Mask/Merge Unit Disclosure Number: IPCOM000051563D
Original Publication Date: 1981-Feb-01
Included in the Prior Art Database: 2005-Feb-10

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Schaughency, MF [+details]


Certain computer architectures include instructions which utilize or need a rotate and mask/merge unit. This CPU unit takes an operand, rotates it a specified amount (0 to 32 bit) positions (bits shifted out being shifted in the opposite end), and then, under control of a mask of ones and zeros, gates out bits of the rotated word where the mask is ones, and gates out bits of a second operand (forced zeros for some instructions) where the mask is zeros. The possible combinations of shift amount, mask configuration, and data inputs could be very large, which initially discouraged any attempt to detect picked up or dropped data bits.