Address Mark Recognition Circuit
Original Publication Date: 1981-Feb-01
Included in the Prior Art Database: 2005-Feb-10
The address mark recognition circuit constitutes an improvement on [*] and in particular allows the file data synchronizing circuit of [*] to correctly synchronize on address marks without being influenced by the variable frequency oscillator 42 erroneously getting into synchronism. The recognition circuit is particularly concerned with the magnetic sector 100, shown in Fig. 2, which includes the following fields: gap 1, VFO sync, AM (address mark), ID, CRC, gap 2, data sync field, AM (address mark) and data. The field 100 is located on magnetic disk 102, shown in Fig. 1. Fig. 3 duplicates most of the circuitry of [*] but with the lines 112, 46, 44, 107, 68, 105 and 114 being brought out and with the counter 56 of [*] being replaced by the bit-latch circuitry 56A, and Fig.