Browse Prior Art Database

Passivation Process for Semiconductor Device with Fusible Link Redundancy

IP.com Disclosure Number: IPCOM000051734D
Original Publication Date: 1981-Mar-01
Included in the Prior Art Database: 2005-Feb-10

Publishing Venue

IBM

Related People

Authors:
Davis, DE Motsiff, WT Poulin, NR [+details]

Abstract

Semiconductor memory devices incorporating fusible link redundancy are provided in which terminal metallurgy is applied to devices prior to testing and fuse blowing. A subsequently applied polyimide passivating layer protects exposed metallurgy and acts as a blocking mask against alpha particle radiation.