Bit Line Selection Circuit for Programming Level Voltages in an Electrically Alterable Read Only Storage
Original Publication Date: 1981-Mar-01
Included in the Prior Art Database: 2005-Feb-11
A bit line selection circuit uses low level (5-volt) dynamic logic gating on the memory array for selectively routing programming level voltages and thereby avoids the transmission of programming level voltages through the bit line decoder where a voltage-initiated device breakdown might occur. 0n the array, the nodes subjected to high voltage may be protected using a ring of metallization to prevent breakdown.