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Adder Architecture Disclosure Number: IPCOM000051805D
Original Publication Date: 1981-Mar-01
Included in the Prior Art Database: 2005-Feb-11

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Williams, TA [+details]


Adder architecture is disclosed having a reduced computation time for two additions of three binary operands. A pair of adjacent bits from adjacent positions in each of three binary operands are input to a pair of one-bit carry save adders whose outputs are cascaded into a two-bit carry propagate adder with a carry look-ahead feature. The resultant operation of two additions of three operands can be carried out for a single-addition-equivalent delay time of approximately one-third the delay time of a conventional one-bit carry propagate adder.