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Read Write Dynamic Memory Using Two Devices Per Cell and Having Internal Refresh

IP.com Disclosure Number: IPCOM000051817D
Original Publication Date: 1981-Mar-01
Included in the Prior Art Database: 2005-Feb-11

Publishing Venue

IBM

Related People

Authors:
Wu, PT [+details]

Abstract

A dynamic read/write memory (Fig. 1) has an array 1 of bit-storage cel 11 each having two field-effect transistors (FETs) 111 and 112 having their sources both coupled to a storage capacitor 113. Capacitor 113 is also coupled to a supply voltage 114.