Common Storage Accessing for Multiple Microprocessor System
Original Publication Date: 1981-Mar-01
Included in the Prior Art Database: 2005-Feb-11
A system having multiple microprocessor subsystems 1, 2, 3 (Fig. 1) accesses a common storage 4 over data and address busses 41, 42 whenever this storage is selected by a dot-OR control line 43. To avoid contention for storage cycles, each subsystem 1, 2, 3 uses interconnected enable outputs EN and inhibit inputs IN1, IN2 to enforce a priority hierarchy.