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Minimal Test Set Calculation

IP.com Disclosure Number: IPCOM000051880D
Original Publication Date: 1981-Mar-01
Included in the Prior Art Database: 2005-Feb-11

Publishing Venue

IBM

Related People

Authors:
Roth, JP Savir, J [+details]

Abstract

The number of tests computed to detect any of a given set of failures i a logic design - chip, cardboard- in very large-scale integration (VLSI) constitutes a serious problem. As the size of the complexity of the logic increases, the number of tests for conventional test generators seems to grow exponentially. A method is described which, in a reasonable increase in computation, achieves a minimal set of tests to detect a given set of failures. The method is heuristic so that a minimum is not guaranteed, but it is minimal in that it contains no redundant tests; experiments indicate substantial reductions over previous methods.