Cell Design for Masterslice Logic Chips
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11
This masterslice cell design has first level metal lines passing direct over active devices formed in a silicon substrate, permitting direct contact of the lines to the inputs or outputs in the active devices. This cell design is particularly useful for manufacturing Schottky transistor-transistor logic (TTL) cells. Improved wirability and density is achieved with automatic wiring programs.