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Cell Design for Masterslice Logic Chips

IP.com Disclosure Number: IPCOM000051913D
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11

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Related People

Carpenter, LC Hickson, JB Lallier, KW Malone, EK Parent, RM Patel, PT [+details]


This masterslice cell design has first level metal lines passing direct over active devices formed in a silicon substrate, permitting direct contact of the lines to the inputs or outputs in the active devices. This cell design is particularly useful for manufacturing Schottky transistor-transistor logic (TTL) cells. Improved wirability and density is achieved with automatic wiring programs.