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Bus Attachable Loop Memory Disclosure Number: IPCOM000051926D
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11

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Nestork, WJ [+details]


This main memory storage system takes advantage of the processing capability of microprocessors and serial memory storage devices to perform memory housekeeping functions independently from a central processing unit (CPU). The memory controller includes input and output buffers which interface with a CPU or system channel and has system-independent control and addressing logic for the storage of data in main storage.