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Programmable Arithmetic/Logic Circuit

IP.com Disclosure Number: IPCOM000051930D
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11

Publishing Venue

IBM

Related People

Authors:
Bechade, RA Hoffman, WK [+details]

Abstract

This programmable, minimum delay FET logic circuit forms the basis for 2-bit subunit for providing arithmetic and logic functions. The circuit can be used to provide a ripple carry adder or all 16 2-input logic functions as determined by the state of a number of control lines.