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Browse Prior Art Database

Variable-Length Storage Cycle

IP.com Disclosure Number: IPCOM000051943D
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11

Publishing Venue

IBM

Related People

Authors:
Dvorak, TJ Dwyer, H [+details]

Abstract

It is intended to provide a host processor, cache or I/O with maximum storage availability and minimum amount of interference. To obtain the maximum access rate, the array cycle times are overlapped to give an effective access time which is much faster than the actual access time of the array. The data is buffered in the storage controls before it is forwarded to the host. This allows simultaneous transmission of the data to the host and checking the data for single or multiple bit errors. If a single bit error occurs, a flag is raised to the host and the storage cycle is increased the amount of time necessary to correct the single bit error and retransmit it to the host. Array clocking remains unaffected by error conditions through the use of multiple storage data registers, thus simplifying clocking logic.