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Dual dielectric layers are provided for integrated circuits by a proces which does not increase the number of resist masking levels.
English (United States)
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Dual dielectric layers are provided for integrated circuits by a proces which
does not increase the number of resist masking levels.
The first level metal pattern is defined followed by the formation of
interconnecting metal studs by any suitable procedure. A thin blanket layer of
silicon nitride is deposited at low temperature from a plasma, followed by a
quartz layer such that the quartz surface is the same height as the studs. The
surface is then planarized by coating it with a layer of resist or polyimide. The
structure is then dry etched in a plasma which removes quartz and resist or
polyimide at about the same rate, with the etching continued until the nitride is
removed from the top of the studs. The second level metal pattern is then formed
by standard processing.