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High Performance FET Technology Disclosure Number: IPCOM000051972D
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11

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Jambotkar, CG [+details]


A method is described for realizing FET devices having thick insulator islands beneath nearly all of the source/drain region in a self-aligned manner. In addition, the thin gate oxide of the FET is self-aligned with respect to source/drain. Parasitic capacitances are substantially reduced by such an arrangement.