Browse Prior Art Database

High Performance FET Technology

IP.com Disclosure Number: IPCOM000051972D
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11

Publishing Venue

IBM

Related People

Authors:
Jambotkar, CG [+details]

Abstract

A method is described for realizing FET devices having thick insulator islands beneath nearly all of the source/drain region in a self-aligned manner. In addition, the thin gate oxide of the FET is self-aligned with respect to source/drain. Parasitic capacitances are substantially reduced by such an arrangement.