Browse Prior Art Database

Multi Function Latch

IP.com Disclosure Number: IPCOM000051977D
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11

Publishing Venue

IBM

Related People

Authors:
Banker, DC Park, SJ Wong, RC [+details]

Abstract

Conventional PLA latch schemes involve multiple mask changes using additional area. By using fixed true-complement circuits and an AOI circuit as a buffer between two OR array outputs (alpha and beta) and a polarity hold latch input (Fig. 1), 96 or more logic functions can be generated by first level metal personalization. This latch scheme brings out one extra logic level which allows more flexible PLA design at no cost in silicon area. Fig. 1A depicts the conventional PLA design. Fig. 1B depicts the PLA design in accordance with the disclosed technique.