Net Synthesis and Device Recognition for Layout Verification
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11
In VLSI (very large-scale integration) designs, graphic data cannot be efficiently manually verified because of the volume amount of data. It is very difficult and time consuming to correlate graphic data to the original logic circuits. To manually verify VLSI layouts is in a practical sense beyond human mental capacity. The only way is to rely on computer aids.