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Testing Method for Mixed Storage Logic Chips Disclosure Number: IPCOM000051985D
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11

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Geprags, W Mozdzen, J Tandjung, H Warmers, R [+details]


For integrated circuits operating at very high speed it is necessary to accommodate the storage part and the logic part on the same chip to avoid long off-chip delays, and to leave out the LSSD (level sensitive scan design) latches preceding and following the storage part, which otherwise would be necessary for chip testability.