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Enhanced Performance "AND" ROM

IP.com Disclosure Number: IPCOM000052002D
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11

Publishing Venue

IBM

Related People

Authors:
Zbrozek, JD [+details]

Abstract

In an FET read-only storage of the series string or "AND array" type, i which programming is accomplished through selective enhancement/depletion implantation, improved interrogation speed is realized when the FETs which serve as memory cells are implanted so that the enhancement-mode devices have a threshold of zero volts and the depletion devices are additionally shifted negatively. Sensing is accomplished by a race to drive a latch against a reference waveform having a time constant nominally half of that of the string when the interrogated FET is a depletion-mode FET.