Paged Read Only Storage
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11
In an FET read-only store of the series string or "AND array" type, one of the axes of decode required to interrogate the array is formed by connecting together the gates of like positioned transistors in each of many series strings within the array. The result of this connection is a set of networks exhibiting large capacitive loadings, and which are difficult to drive quickly with small economical circuits. It is herein proposed that the address bits associated with this particular, heavily loaded axis of decode be grouped together and considered as high-order or "page-select" bits, such that these address bits are allowed to change only on dedicated "page-select" cycles.