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Browse Prior Art Database

Edge Triggered Set Reset Latch

IP.com Disclosure Number: IPCOM000052005D
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11

Publishing Venue

IBM

Related People

Authors:
Cassidy, BM Combs, SG [+details]

Abstract

The drawing shows a reverse-logic latch circuit of FETs which is trigge on the trailing edge of the set signal.