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An output buffer for a dynamic programmed logic array (PLA) permits hig switching speeds with low power dissipation and reduces susceptability to capacitively coupled noise.
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Output Buffer for a Programmed Logic Array
An output buffer for a dynamic programmed logic array (PLA) permits hig
switching speeds with low power dissipation and reduces susceptability to
capacitively coupled noise.
Referring to the figure, the buffer circuit is connected to node N1, which is the
output node for an OR circuit array 8 of the PLA 10. Initial precharging of the
node N1 is effected by a transistor T1 that is connected to a supply V(DD) and is
controlled by a gate signal 0R (see waveform). When node N1 is charged, node
N2 is grounded through the transistor T2. With node N2 at ground potential,
transistor T6 is turned off and depletion load device T5 conducts to charge the
output node N3 to the level V(DD).
When 0R shifts to a low level (see waveform), node N1 remains high DD)) as
does the output node N3. When B2 goes high (see waveform), the input signals
(IN1 to INM) to the OR array 8 control the state of the output node N3. If any of
the input signals IN1 to INM is high, node N1 is discharged to ground and node
N2 is charged through transistor T3 to a threshold drop below V(DD) as a result
of the connection through depletion load device T4. The rise in level of node N2
turns on transistor T6, grounding the output node N3.
If all of the signals IN1 to INM are at a low level, then node N1 is not
discharged and transistor T2 continues to conduct, holding node N2 at a low
level. With node N2 at a low level, transistor T6 remains nonconducting and