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The figure illustrates a circuit for synchronizing two clocking systems in a particular clock transition using a minimum amount of logic and preventing metastability uncertainty.
English (United States)
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Clocking System Synchronization
The figure illustrates a circuit for synchronizing two clocking systems in a
particular clock transition using a minimum amount of logic and preventing
Clock System A is asynchronous with Clock System B. System A produces a
pulse indicating that data or conditions are ready to be manipulated or sampled
by System B. In the system, data located in a register clocked by clocking
System A is to be written into a RAM (random access memory) clocked by
clocking System B. A further limitation is that writing into the RAM is strictly
controlled and can only occur during a positive transition of System B master
clock (clock M).
In operation, an asynchronous pulse from System B becomes active and sets
a latch called Write Required. The output of the Write Required latch is an input
to a 'D' type flip-flop called FF'A' which provides the metastability settling time
(arbitrarily selected to be ten times the latchback delay) and will be either set or
reset before clock M makes the next negative to positive transition.
If FF 'A' is set, the next negative-to-pos. transition of clock M sets FF 'B',
producing the write cycle. If FF 'A' is not already set, it will be on the second
negative to positive transition of clock M. This enables the setting of FF 'B' on the
third negative-to-positive transition. The Write Required latch is reset by FF 'B'
active and clock A (first 1/3 of clock M) to allow the Write Required latch to...