Computer Timing Verifier
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11
A vital requirement for an LSI or VLSI computer is that its timing constraints not be violated. The timing constraints are expressed by means of clock times associated with various registers; the violations are effected by too long delays between these registers. Straightforward implementations of timing verifiers require excessively frequent access to secondary storage, which exacerbates running time.