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Embedding Interleaved With Constraints Disclosure Number: IPCOM000052104D
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11

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Related People

Frisiani, AL Kurtzberg, JM Roth, JP [+details]


A method is outlined for the embedding - interleaving placement and routing - of a logic design on a chip or a set of chips on a board. These embeddings are subject to constraints, such as timing, power dissipation, distances to I/O pins, delta-I effects, etc., and such checking operation is interleaved with the embedding.