Embedding Interleaved With Constraints
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11
A method is outlined for the embedding - interleaving placement and routing - of a logic design on a chip or a set of chips on a board. These embeddings are subject to constraints, such as timing, power dissipation, distances to I/O pins, delta-I effects, etc., and such checking operation is interleaved with the embedding.