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Arithmetic and Logic Unit Hardware Arrangement for Simultaneous Floating Point Multiply Then Add Operations

IP.com Disclosure Number: IPCOM000052114D
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11

Publishing Venue

IBM

Related People

Authors:
Cannon, JW Jones, JF Villante, AE [+details]

Abstract

High speed multiplication of 64-bit operands is performed utilizing a 16-bit processor. A Floating Point (FP) Multiply instruction merits special implementation consideration since both its frequency of execution and total execution time are relatively large numbers, thus insuring that an FP multiply instruction is a major contributor to a system's Average Instruction Time (AIT).