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LSSD Testable J/K Flip/Flop

IP.com Disclosure Number: IPCOM000052128D
Original Publication Date: 1981-May-01
Included in the Prior Art Database: 2005-Feb-11

Publishing Venue

IBM

Related People

Authors:
Gretchev, V [+details]

Abstract

A J/K flip-flop which is LSSD (Level Sensitive Scan Design) testable is described. This J/K flip-flop is composed of a number of shift register latches (SRLs) which serve dual purposes, namely, as substitutes for the gates normally used to implement a J/K flip-flop and also to permit the feedback paths of the flip-flops to be broken, removing the sequential nature of the device, to permit combinatorial testing in conformity with LSSD test guidelines by individual exercising of the AND gates, for instance, by computerized testing programs.