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Hermetic Seal Process for Multilevel Metallurgy Disclosure Number: IPCOM000052157D
Original Publication Date: 1981-May-01
Included in the Prior Art Database: 2005-Feb-11

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Bartush, TA Brooks, GA Chiu, GT [+details]


Hermetically sealed, multilevel metallurgy for integrated circuits is provided using quartz layers that are thinner than the metal lands. Quartz layer 1 is deposited on substrate 2 to about one half the thickness of metal layer 3 (Fig. 1). A planarizing layer 4 of photoresist is applied such that the ratio of the thickness delta 2 to delta 1 is larger than it would be if quartz layer 1 was of equal thickness to metal layer 3 (Fig. 2).