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Structure Using FET Selective Etching to Produce Small Dimensions Disclosure Number: IPCOM000052171D
Original Publication Date: 1981-May-01
Included in the Prior Art Database: 2005-Feb-11

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Bartholomew, RF Revitz, M Shepard, JF [+details]


A method is described which uses selective etching to form small dimensioned regions in an integrated circuit structure. The method involves, where an FET is to be produced, depositing an intrinsic polysilicon layer 8 on the gate silicon dioxide layer 9 covering a silicon substrate 10, followed by either a silicon nitride or silicon oxynitride deposited layer 11 on the layer 8, as shown in Fig. 1.