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High Performance Field Effect Transistors Disclosure Number: IPCOM000052187D
Original Publication Date: 1981-May-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 3 page(s) / 76K

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Jambotkar, CG: AUTHOR


A method is described for fabricating high-performance enhancement and depletion field-effect transistors (FETs).

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High Performance Field Effect Transistors

A method is described for fabricating high-performance enhancement and depletion field-effect transistors (FETs).

Starting with a 20-100 ohm-cm pi type silicon substrate 2, an approximately 600 Angstroms thick SiO(2) layer 4 is grown on the substrate through thermal oxidation. On top of the SiO(2) layer 4, a 1000 Angstroms thick Si(3)N( layer 6 is obtained through chemical vapor deposition (CVD). Using photolithography and, preferably, reactive ion etching (RIE), the Si(3)N(4) and SiO(2) layers are then selectively etched. ,This is followed by etching he exposed silicon to a depth of about 5000 Angstroms as shown in Fig. 1. Retaining the photoresist masking pattern, a suitable dose of boron is ion-implanted about 4000 Angstrom below the exposed silicon surface to realize P regions 7.

After growing about 1 Mum thick thermal SiO(2) 8 in the exposed silicon regions, the remnant portions of the Si(3)N(4) layer 6 and SiO(2) layer 4 are removed so as to obtain the structure shown in Fig. 2. Approximately 6000 Angstroms and 4000 Angstroms thick layers of N/+/ doped polysilicon 10 and SiO(2) 12, respectively, are now deposited through CVD. The N/+/ doping of the polysilicon layer 10 is preferably realized using ion implantation techniques. Patterns are successively etched in SiO(2) layer 12 and polysilicon layer 10 using photolithography. Fig. 3 illustrates the structure at this stage of processing.

Through a heat cycle, the N/+/ dopant in polysilicon is driven into the underlying substrate to a junction depth of about 4000 Angstroms so as to obtain N/+/ regions 16. Through CVD, a suitable thickness of Si(3)N(4) layer 20 is next deposited such that the distance "T" identified in Fig. 4 is 0.3-0.5 Mum. Using the directional etching property of RIE, the Si(3)N(4) layer 20 is etched. At the end of this RIE, the substrate 2 is exposed at the region "T". Because of the directionality in RIE, the Si(3)N(4) layer 20 at the sidewalls of the polysilicon islands 10 remains practically unharmed, as illustrated in Fig. 5.

Using a non-critical, block-out mask of...