Browse Prior Art Database

Error Detection for all Errors in a 9 Bit Memory Chip

IP.com Disclosure Number: IPCOM000052208D
Original Publication Date: 1981-May-01
Included in the Prior Art Database: 2005-Feb-11

Publishing Venue

IBM

Related People

Authors:
Kelleher, DF [+details]

Abstract

Five memory chips that each have a 9-bit data bus are combined to store a memory word of 32 data bits and 8 error correction code (ECC) bits for conventional single error correction and double error detection. Four chips each hold 8 data bits and, in addition, hold one parity bit for these 8 data bits. One chip holds the 8 ECC bits and, in addition, holds a parity bit for the ECC bits. The ECC logic is combined with parity logic to detect any combination of errors on a single 9-bit chip.