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Fast Settling Sample and Hold Circuit

IP.com Disclosure Number: IPCOM000052241D
Original Publication Date: 1981-May-01
Included in the Prior Art Database: 2005-Feb-11

Publishing Venue

IBM

Related People

Authors:
White, DB [+details]

Abstract

Amplifier A2, resistor R3 and holding capacitor CH are connected to for an inverting integrator. When switch S1 is closed, the circuit integrates an error signal which causes the holding capacitor to charge up to the desired level. Since the non-inverting input of amplifier A2 is connected to ground, its output voltage (EO) is equivalent to the voltage stored on the holding capacitor.