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Variable Speed I/O Instructions

IP.com Disclosure Number: IPCOM000052253D
Original Publication Date: 1981-May-01
Included in the Prior Art Database: 2005-Feb-11

Publishing Venue

IBM

Related People

Authors:
Crooks, TL Schoen, RL [+details]

Abstract

Control circuitry for channel control logic is responsive to the decode of the port address specified by the I/O instruction for generating either normal or fast-rate synchronizing signals for use during the execution of the I/O instruction. I/O devices having different speed requirements of limitation are accommodated by loading the appropriate port address into a work register which is used for I/O instructions to particular I/O devices. The channel control logic decodes the port address to determine the appropriate execution speed. By this arrangement, no special lines are required from the I/O device attachments to select the speed of execution.