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Controllable Process for Fabricating an LDDFET Device Using Preferential Etching Disclosure Number: IPCOM000052340D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11

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Bartholomew, RF Revitz, M Shepard, JF [+details]


Various techniques have been used to fabricate the lightly doped drain FET (LDDFET) devices where N regions are interposed between the heavily doped N+ source and drain regions and the P gate region. However, it may be difficult to form uniform width spacers across a wafer and to reproduce the width from run to run using reactive ion etching procedures. An alternative method of forming the narrow N regions is more controllable. The process is as follows: 1) After gate silicon dioxide layer 10 thermal growth on silicon substrate 11, a polysilicon layer 12 is deposited thereon. A Si(3)N(4) layer 13 is deposited upon layer 12. 2) Photolithography techniques are used to mask and to selectively reactive ion etch the Si(3)N(4) layer 13 everywhere but over the FET gate regions.