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Binary Multiplying Arrangement Disclosure Number: IPCOM000052372D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11

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Bazlen, D Chilinski, H Getzlaff, KJ Hajdu, J [+details]


This arrangement uses a simple short-cut method, by means of which two multiplier bits are simultaneously processed from left to right, beginning with the most significant and ending with the least significant multiplier bit. Alternatively, if the significant one of the two bits requires the addition of twice the multiplicand MD to the partial product, the arrangement reverts to the very simple method of processing only one MR bit at a time. This method eliminates the preparation and storage of twice the MD as well as the addition of the shifted MD to the partial product, for which purpose additional time and hardware and the addition of one bit to the data path widths and the MD register would otherwise be required.