Browse Prior Art Database

PLA with Product Term Test Circuit

IP.com Disclosure Number: IPCOM000052374D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11

Publishing Venue

IBM

Related People

Authors:
Chu, WM Colao, R [+details]

Abstract

A programmable logic array (PLA) can be personalized by making laser welds at selected crosspoints of the array. A circuit test is made after each product term is personalized and all other product terms are temporarily deleted. Some of the product terms in the OR array apply data to a latch which performs a logical AND function. The data content of the latch can be monitored either at the primary output or through the LSSD scan path. However, the inputs to the latch can not be tested at the PLA output because a signal that might be applied by the product term line for test is inhibited by the 0 logic state of each other input to the AND function. An auxiliary circuit provides a supplemental input to the AND latch on the associated product term lines so that a coincidence of signals permits testing these product terms.