Browse Prior Art Database

Fast Send Count

IP.com Disclosure Number: IPCOM000052404D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11

Publishing Venue

IBM

Related People

Authors:
Frye, HE [+details]

Abstract

The operation of send count and receive count instructions is describe in U.S. Patent 4,177,513, beginning on column 23, line 12 and ending on column 25, line 10. During operation of a send count instruction, if the count is greater than or equal to the limit, remove cycles are taken so as to dequeue waiting task dispatching elements (TDEs) from the counter and enqueue them to the task dispatching queue (TDQ). Once this is accomplished, the dispatch cycles are activated and a task switch occurs whereby, assuming that the highest priority waiting TDE becomes the highest priority TDE on the TDQ, control is then returned to the previously unsatisfied receive count instruction of that TDE.