Complementary Dynamic Memory Cell
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
A semiconductor memory cell is described herein which is a modification of the non-destructive read-out dynamic memory cell described in U.S. Patent 4,085,498. The memory cell in U.S. Patent 4,085,498 depends on avalanche breakdown or punch through which is difficult to control and may introduce reliability problems; hence, it is desirable to write the memory cell with other methods. Therefore, a write gate has been added to the memory cell. This write gate controls a hole current path, which is underneath the memory gate, from the substrate to the hole storage region. Thus, a more controllable and reliable method for writing the memory cell to "on" or "off" state is obtained.