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Asymmetric Execution/Decoder Concurrence

IP.com Disclosure Number: IPCOM000052472D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11

Publishing Venue

IBM

Related People

Authors:
Agerwala, TK Rechtschaffen, R [+details]

Abstract

A 2-at-a-time fixed-point E-unit can be implemented at a much lower cos than a 2-at-a-time decoder. An infinite cache flow analysis shows that a balance between decoder and %-unit concurrences is most effective. However, finite cache penalties have become a larger portion of achievable cycles per instruction, and a productive work opportunity exists if the decoder can continue to process instructions during the cycles following an operand miss. The scheme set forth enhances the cycles saved by implementing an E-unit with higher concurrency than the I-unit (as shown in Fig. 1).