Address Generate Interlock Avoidance for Branch Instructions in a Branch History Table Processor
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
High performance processors typically have separate decoding and execution units which operate concurrently in a pipelined configuration. The decoder contains an address adder for operand address and branch-target address calculations, while the execution unit contains the necessary logic for updating the contents of the general-purpose registers (GPRs).