LSSD Compatible Scheme for Creating Clocks Having Pulse Widths Which Are Less Than That Transmittable on TCMs
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
Since the minimum clock pulse transmittable on a TCM (Thermal Conductin Module) is expected to be larger than that demanded by future systems with small cycle times, there may soon be a need for a clock generation scheme capable of creating faster clocks. The following describes an LSSD (Level Sensitive Scan Design)-compatible scheme for generating on chip clocks (by "clock chopping" which run at twice the frequency of the off-chip clocks. The cost of such a clock generation scheme is 19 OR/NOR gates, 1 SXL (Shift-Register Latch), 1 I/O Pin, and the writing of 1 chip test test-case.