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In the design and testing of logic several complex algorithms are brought into play. Here three techniques simplifying some of these operations are described.
English (United States)
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Logic Design Simplification
In the design and testing of logic several complex algorithms are brought into
play. Here three techniques simplifying some of these operations are described.
The first technique is an extension and at the same time simplification of the
P* process [*] for reducing regular logic in its acyclic portions to two-level
equivalents' The difficulty encountered with P* is that for large designs, the size
of the two-level equivalent circuits becomes very excessive. Here, as the P*
process is being unfolded, changing many levels to two levels, a count is kept on
the size of the arrays being formed; when this count exceeds a bound specified
by the user, the process is terminated locally, the portion of the design thus far
reduced is rendered in the final transformation as its own two-level form, and its
inputs are treated as outputs for the operation of P* on subsequent portions of
the circuit. In this manner large designs can always be rendered into
assemblages of two-level designs, depending upon the user, for subsequent
processing such as factoring and implementation [*]. This process is termed
In optimizing logic [*], a critical step is the determination of redundancy with
respect to a cover (a PLA). This is used as in approximations, such as SHRINK.
The following (second) method is a substantial improvement over previous
Let e be a cube and E = [e1, ..., er], a set of cubes;
then e is redundant with respect to...