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Recessed Oxide Isolation Etch Bias Improvement

IP.com Disclosure Number: IPCOM000052504D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11

Publishing Venue

IBM

Related People

Authors:
Frederick, R Rozich, WR Saraf, LH Waite, TW [+details]

Abstract

VLSI (very large-scale integration) designs require tighter ground rule and smallest etch bias capability. Recessed oxide isolation (ROI) processing is included. This is required to achieve smaller ROI width capability, resulting in circuit density enhancement. The ROI trench is formed by etching nitride-oxide-silicon after the photoresist image has been formed by standard lithography techniques. A resist side wall slope of approximately 80 degrees is necessary to produce minimal ROI etch biases. Only then can a ROI nitride-oxide-silicon trench be processed with a single step CF(4) dry etch process, resulting in acceptable ROI etch bias. However, if the resist slopes cannot be maintained nearly vertical, then the etch bias produced with this dry processing is larger for the ROI trench, which is not acceptable.