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Stress Level Gage for Chips

IP.com Disclosure Number: IPCOM000052510D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11

Publishing Venue

IBM

Related People

Authors:
Fredriks, RM [+details]

Abstract

Chip placement and flip-chip joining have caused quartz damage to occur on the final product. This strain-gage technique here would allow one to monitor the stress level in the quartz layer during and after these exposures.