Paging from Multiple Bit Array Without Distributed Buff
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11
A technique is described whereby a multiple bit output array chip transfers its output at a single transfer without requiring distributed logic buffering. The transferred bits are then distributed across different ECC (error correcting code) words via address selection of different locations in the full page buffer of the array controller.