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Data Out Path with Minimum Delay

IP.com Disclosure Number: IPCOM000052549D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11

Publishing Venue

IBM

Related People

Authors:
Heimeier, HH Klein, W Najmann, K Wernicke, FC [+details]

Abstract

Storage array chips with storage cells of bipolar transistors are increasingly provided with latches in the output lines, so that the data read during the read cycle are available for a longer time to the data processing system interacting with the storage. As these latches are positioned in the output data path, they must be very fast, in order to reduce additional delays to a minimum. However, the great number of latches necessary for this purpose require much chip area and lead to very high power dissipation of the storage array. In the illustrated circuit the space requirements are reduced by latch transistors which can be integrated with the transistors of the read amplifier. The switching speed is essentially governed by the speed of the read amplifier, and there is no additional gate delay for the latch function.