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This scheme provides a test of both the addressing circuits 10 and storage cells 12 of a memory 14 with the storage and reading out of two code words A and B in each word location of the memory.
English (United States)
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Two Pass Array Test Method
This scheme provides a test of both the addressing circuits 10 and storage
cells 12 of a memory 14 with the storage and reading out of two code words A
and B in each word location of the memory.
Each address in the memory is accessed and the parity of the memory
address is determined. If the odd parity of the address is one, then a pattern A of
alternating 1's and 0's is placed in the word location accessed by that memory
address. If the odd parity of the address is zero, then a second test pattern B,
which is a complement of the first test pattern, is placed in the word location.
This goes on until all the memory locations are full. With the memories full, data
is read out of the memory, memory location by memory location. After
completion of the first read and write cycle, a second read and write cycle is
performed. This time an address with odd parity of one receives the second
pattern B, while the storage location of an address with an odd parity of zero
receives the first pattern A. After completion of reading and writing of this second
pattern, it can be determined whether any of the memory locations contain stuck
ones or zeros because each bit location has received a one and a zero and the
type pattern can be compared against address parity to determine if the proper
pattern was stored in the addressed location.
In addition to reducing the number of passes through the memory, this
scheme also reduces the number of data patterns t...