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Trigger Arrays Using Shift Register Latches

IP.com Disclosure Number: IPCOM000052590D
Original Publication Date: 1981-Jun-01
Included in the Prior Art Database: 2005-Feb-11

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Das Gupta, S [+details]


This arrangement of latches in an array permits the latches of the arra to be used in a shift register mode of operation during test with a minimum of added structure.